1. Field of the Invention
This invention relates to electronic matrix array devices comprising crossing sets of row and column conductors and matrix elements adjacent the intersections between the sets of row and column conductors, at least some of which are two terminal thin film non-linear impedance elements connected between intersecting row and column conductors. The invention relates also to systems incorporating such matrix array devices and methods of operation of such systems.
The invention is concerned particularly, but not exclusively, with such matrix array devices which, more particularly, are data storage devices or active matrix electro-optic display devices.
2. Description of the Related Art
Data storage devices employing a row and column array of memory cells formed by sets of intersecting row and column conductors are well known. Several different types exist using various circuit elements placed at the intersections to represent the storage of a logic 1 or logic 0. For example, SRAMS using bistable latches, DRAMS using capacitors, ROMs using diodes, and PROMS using diodes and fuseable links. Data is read from, and in programmable types is written into, the array by means of address decoders and multiplexers.
Such data storage devices are commonly fabricated as integrated circuits having monocrystalline semiconductor substrates. It has been proposed, alternatively to fabricate data storage devices using thin film technology to form two-terminal thin film non-linear impedance elements, for example amorphous silicon diodes and more recently MIM (metal-insulator-metal) impedance elements, on an insulating substrate such as glass or plastics. This is described, for example, in published foreign applications GB-A-2066566 and EP-A-376830 respectively. The cost of the substrates in such devices is considerably less than, for example, the more crystalline semiconductor substrates used in conventional silicon devices. Moreover much larger areas can be employed for the data storage array. The large area electronics technology necessary for fabricating thin film devices over comparatively large areas of low-cost substrates is now well established, having been employed for example in active matrix display devices. These factors, together with the potential for such devices to store large amounts of data without recourse to electro-mechanical means for data read-out, as required for example by CD-ROM systems and optical data memory card systems, render them suited to a wide variety of uses and particularly in portable information systems.
Access to the data stored in the array can be accomplished by a peripheral circuit comprising column and row decoder circuits which provide an interface between an input address signal and a data output line. The function of the row decoder circuit is to select an individual row conductor by applying a select potential to that row conductor, according to an address value supplied to a common address bus to which individual stages of the decoder circuit, each associated with a respective conductor, are connected. The function of the column decoder circuit is to select individual column conductors according to an address value and to output the bit of information held at the intersections of the selected row and column conductors. The number of connections between the memory cell array and the peripheral circuit is determined by the number of row and column conductors. For example, with a 1M bit array at least 2049 connections would normally be required, comprising 1024 row conductor connections, 1024 column conductor connections and 1 data-output connection. It is obviously desirable therefore to integrate this peripheral circuit with the array, especially with data storage devices such as memory cards which are not permanently connected in a circuit. Commonly, address decoding and output encoding circuits utilise FET switching elements. When used with monocrystalline silicon memory cells, these FET circuits can readily be integrated with the memory cell array by common fabrication processes. However, in the case of memory cell arrays comprising thin film diode or MIM devices, the integration of FET circuits therewith would entail using fabrication processes different from those required by the memory array, thus complicating manufacture and increasing cost.
In active matrix display devices, such as liquid crystal display devices employing thin film two terminal non-linear elements, the picture elements are at the intersections of sets of row and column address conductors carried on respective, opposing, supports. Each picture element is connected between respective row and column conductors and comprises a two terminal non-linear impedance element acting as a switch, for example a MIM, back to back diodes or a diode ring structure, connected in series with a display element consisting of two opposing electrodes carried on the supports and having electro-optic material sandwiched therebetween. In operation, selection and data signals are applied to the two sets of conductors such that the display elements of one row at a time are charged according to the level of the data signals to produce the desired display effects. Such display devices are well known and widely documented. By way of example reference is invited to published GB-A2129183 and U.S. Pat. No. 4,413,883. It is customary for the peripheral selection and data signal drive circuits to be fabricated separately from the display panel and for their outputs to be connected to the address conductors through interconnection devices. When large numbers of address conductors are involved, as is the case for many datagraphic or video display devices which comprise an array of, say, 200 by 300 picture elements, the number of interconnections required can become difficult, even when the drive circuits are in the form of integrated circuits which are mounted directly on the display panel using chip-on-glass technology.
Examples of memory array devices and display array devices using thin film diodes and the like in which the decoder circuits are integrated on the same substrate as the arrays are described in U.S. Pat. Nos. 4,782,340 and No. 4,807,974, respectively. The decoder circuits therein comprise diode-resistor type logic gate circuits. A problem with such circuits is that it is difficult to provide reliably the necessary resistors in thin film form having well controlled and accurate resistances. Moreover, the output from this type of logic circuit is transient, having a duration only corresponding to that of the applied input address signal.
It is an object of the present invention to provide a matrix array device of the kind described in the opening paragraph in which at least part of a peripheral addressing circuit can be integrated with the matrix element array on the same substrate as used for the non-linear devices of the array, and without undue complications to the manufacturing process.